4. DS28CN01 and DS2460

The DS28CN01 and DS2460 are secure SHA-1 coprocessors with integrated EEPROM. Ring-series hardware utilises a DS2460 on the ExIO board and a DS28CN01 on the keychip which together are used to validate keychip authenticity.

The Amex board used in Nu systems make use of DS2465 and DS28E15 SHA-256 coprocessors. This page does not currently apply to these.

4.1 Legal Preface

Significant portions of the publicly available datasheets for these coprocessors are redacted. The content on this page is almost exclusively redacted information. Analog Devices do not offer NDAs to individuals; all content presented here was independently researched.

4.2 Application to Ring

The remainder of this document constitutes a large proportion of the information omitted from the public datasheets, and is not specific to the Ring platform.

The DS28CN01 chip on the keychip has 128 bytes of data pre-populated in the EEPROM. This data is unique per game, and matches the corresponding SXXX_Table.dat table. amDongle uses a random challenge from this file, and a random choice of the four EEPROM pages, then compares this against an anonymous hash.

When the system boots, mxkeychip.exe requests a non-anonymous hash from the DS28CN01 chip using a random challenge. By reading the appropriate page of EEPROM and the unique serial number, a payload matching that which the DS28CN01 used internally can be transmitted to the DS2460 co-processor. E-Secret 2. The 8 bytes corresponding to the secret and the 9 bytes of padding are populated with random bytes, and will be substituted by the DS2460 internally. The resulting MAC is compared, and authentication with the PIC and N2 will only proceed if this preliminary check succeeded.

The secret used for all devices is 2ed76121ddb05f30.

When a keychip has the development flag set, amDongle switches to to a hardcoded challenge and response list. All development keychips use the same user eeprom, which can be found on the keys list page.

4.3 Dallas SHA

Dallas Semiconductor SHA co-processors use a modified variant of SHA-1.

The following pseudocode snippet is adapted from Wikipedia and comparison against the SHA-1 pesudocode on that article should make the modifications clear.

break message into sixteen 32-bit big-endian words w[i], 0 ≤ i ≤ 15

Message schedule: extend the sixteen 32-bit words into eighty 32-bit words:
for i from 16 to 79
    Note 3: SHA-0 differs by not having this leftrotate.
    w[i] = (w[i-3] xor w[i-8] xor w[i-14] xor w[i-16]) leftrotate 1

Initialize hash value for this message:
a = 0x67452301
b = 0xefcdab89
c = 0x98badcfe
d = 0x10325476
e = 0xc3d2e1f0

Main loop:
for i from 0 to 79
    [unchanged]

Produce the final hash value (little-endian) as a 160-bit number:
mac = (e leftshift 128) or (d leftshift 96) or (c leftshift 64) or (b leftshift 32) or a

Specifically, Dallas SHA operates on exactly only “chunk” of message of exactly 64 bytes. It omits the final addition of the chunk hash to the output result. The final hash value is little-endian using the hash value variables in the reverse order to typical SHA; this is equivalent to a bytewise reversal of the hash.

The following python snippet potentially presents the computation of a Dallas SHA more succinctly:

import hashlib, struct
A, B, C, D, E = struct.unpack(">5I", hashlib.sha1(MT).digest())
A = (A - 0x67452301) & 0xffffffff
B = (B - 0xefcdab89) & 0xffffffff
C = (C - 0x98badcfe) & 0xffffffff
D = (D - 0x10325476) & 0xffffffff
E = (E - 0xc3d2e1f0) & 0xffffffff
return struct.pack("<5I", E, D, C, B, A)

4.4 DS28CN01

4.5 Register Map

4.6 User EEPROM [00h to 7Fh],R/W

User EEPROM is structured as 4 pages of 32 bytes. Transfers are performed in blocks of up to 8 bytes at once.

4.7 Secret memory [??],?

The DS28CN01 has 8 bytes of secret memory usable as part of the SHA-1 computation.

I do not currently know which address to write to in order to set this memory, nor do I know how to perform a SHA-1 -> Secret internal transfer.

4.8 Unknown region [90h to 9Fh],?

55555555 55550000 55094200 00000000

4.9 Unique serial [A0h to A7h],R

The DS28CN01 has a read-only guaranteed unique serial number that can be read from this address range, and can be used during SHA computation.

The first byte of this value is always 70h, and the final value is a CRC-8/MAXIM sum of the prior 7.

4.10 Communication mode [A8h],W

Writing a zero to this register sets the communication mode to I2C. Other values are unknown

4.11 Status [A8h],R

Read co-processor status. Bit values:

4.12 Compute MAC [A9h],W

Writing to this address will perform a MAC calculation. The transfer should begin with a single byte describing the operation to perform:

The value of the individual upper four bits is unknown. Operation using 0xD0 will perform a hash using the unique serial number; using 0xE0 will omit the serial number from the input buffer (anonymous hash).

Following the command byte, a 7 byte challenge should be transferred, which will be used as part of the MAC computation.

MACs are computed by concatenating the following sequence of values:

• First 4 bytes of secret
• Selected 32-byte EEPROM page
• First 4 bytes of challenge
• 40h | (page)
• First 7 bytes of unique number, or 7×FFh bytes if omitted
• Final 4 bytes of secret
• Final 3 bytes of challenge

This is exactly 55 bytes, and will be padded to 64 bytes using standard SHA-1 padding. That is, [37h]=80h, [38h-3Dh]=00h, [3Eh]=01h, [3Fh]=B8h.

After requesting computation of a MAC, the Status register should be polled until the engine is no longer reported as busy.

4.13 Output MAC [B0h],R

The output MAC can be retrieved from this address using a 20-byte read.

4.14 DS2460

4.14.1 Register Map

4.14.2 Transfer to secret command [01SSxxxx]

Transfer data to secret SS.

4.14.3 Compute SHA-1 command [10GSSxDx]

Compute SHA-1 using secret SS.

If G is set, a general purpose SHA will be computed, otherwise a Dallas SHA will be computed.

If D is set, the output will be transferred to the MAC buffer after computation.